Clock and data recovery devices with fractional-N PLL

ABSTRACT

The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

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BACKGROUND OF THE INVENTION

The present invention relates to data communication and electricalcircuits.

Over the last few decades, the use of communication networks hasexploded. In the early days of the Internet, popular applications werelimited to emails, bulletin board, and mostly informational andtext-based web page surfing, and the amount of data transferred wasusually relatively small. Today, Internet and mobile applications demanda huge amount of bandwidth for transferring photo, video, music, andother multimedia files. For example, a social network like Facebookprocesses more than 500 TB of data daily.

Clock and data recovery (CDR) devices are used in a wide range ofapplications. For example, to process data received over a communicationnetwork, a receiver relies on its CDR to generate a clock signal basedon the received data. The performance of the receiver relies on theperformance of its CDR and other components. Over the time, there havebeen many different types of CDR designs and implementations, however,they have been inadequate for the reasons explained below. Therefore,new and improved CDR devices are desired.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to data communication and electricalcircuits. More specifically, embodiments of the present inventionprovide a clock and data recovery (CDR) architecture implementation forhigh data rate wireline communication links. In an embodiment, a CDRdevice includes a phase detector, a loop filter, and a fractional-N PLL.The fractional-N PLL generates output clock signal based on output ofthe loop filter. There are other embodiments as well.

According to an embodiment, the present invention provides A clock datarecovery (CDR) device, which includes a first phase detection moduleconfigured to receive digital input signal and determine a differencebetween phases of the digital input signal and an output clock signal.The device additionally includes a loop filter module coupled to thephase detector module and configured to generate a frequency controlword. The device also includes a fractional-N phase lock loop (Frac-NPLL) configured to generate the output clock signal based on thefrequency control word. The Frac-N PLL includes a second phase detectionmodule coupled to a reference clock signal. The Frac-N PLL also includesa charge pump coupled to the second phase detection module. The Frac-NPLL additionally includes an analog loop filter coupled to the chargepump. The Frac-N PLL also includes a sigma delta modulator configured toprocess the frequency control word.

According to another embodiment, the present invention provides a clockdata recovery (CDR) device that includes a first phase detection moduleconfigured to receive digital input signal and determine a differencebetween phases of the digital input signal and an output clock signal.The device also includes a loop filter module coupled to the phasedetector module and configured to generate a frequency control word. Thedevice additionally includes a fractional-N phase lock loop (Frac-N PLL)configured to generate the output clock signal based on the frequencycontrol word, the Frac-N PLL comprising a high-pass filter forprocessing the frequency control word. The high-pass filter has aninverse filter and an anti-aliasing filter.

According to yet another embodiment, the present invention provides aclock data recovery (CDR) device, which has a first phase detectionmodule configured to receive digital input signal and determine adifference between the digital input signal and an output clock signal.The device also includes a loop filter module coupled to the phasedetector module and configured to generate a frequency control word. Thedevice additionally includes a fractional-N phase lock loop (Frac-N PLL)configured to generate the output clock signal based on the frequencycontrol word. The Frac-N PLL has a voltage controlled oscillatorconfigured on a feedforward signal path and a current modedigital-to-analog converter.

It is to be appreciated that embodiments of the present inventionprovide many advantages over conventional techniques. Among otherthings, CDR devices implemented according to embodiments of the presentinvention are smaller and more efficient compared to existing devices(e.g., phase-interpolator or digitally controlled oscillatorimplementations). For example, compared to CDRs with digitallycontrolled oscillators, CDRs with fractional-N PLL have better immunityto various types of coupling noise. Additionally, a fractional-N PLLbased CDR can provide independent gain suitable for the CDR device.

Embodiments of the present invention can be implemented in conjunctionwith existing systems and processes. For example, CDR devicesimplemented with Frac-N PLLs according to the present invention can beused for a wide range of applications and are compatible with existingsystems and architectures. Additionally, CDR devices according to thepresent invention can be manufactured using existing manufacturingprocesses and equipment. There are other benefits as well.

The present invention achieves these benefits and others in the contextof known technology. However, a further understanding of the nature andadvantages of the present invention may be realized by reference to thelatter portions of the specification and attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The following diagrams are merely examples, which should not undulylimit the scope of the claims herein. One of ordinary skill in the artwould recognize many other variations, modifications, and alternatives.It is also understood that the examples and embodiments described hereinare for illustrative purposes only and that various modifications orchanges in light thereof will be suggested to persons skilled in the artand are to be included within the spirit and purview of this process andscope of the appended claims.

FIG. 1 is a simplified diagram illustrating a fractional-N PLL accordingto an embodiment of the present invention.

FIG. 2 provides a small signal model of a multi-modulus divideraccording to embodiments of the present invention.

FIG. 3 is a simplified diagram illustrating a digitally controlledoscillator (DCO) based CDR loop.

FIG. 4 is a simplified diagram illustrating a Frac-N PLL incorporatedinside a CDR loop according to embodiments of the present invention.

FIG. 5 is a simplified diagram illustrating small signal phase domainmodel of a CDR loop with a DCO.

FIG. 6 is a simplified diagram illustrating a small signal model ofFrac-N PLL functioning as a DCO according to embodiments of the presentinvention.

FIG. 7 is a plot illustrating CDR error transfer functions comparingideal DCO and actual DCO implementation (e.g., with Frac-N PLL) with apole that contributes to undesired error transfer function peaking.

FIG. 8 provides plots illustrating CDR error transfer function peaking(top) and Frac-N PLL jitter (bottom) as function of Frac-N PLLbandwidth.

FIG. 9 is a simplified diagram illustrating a small signal model for aFrac-N PLL according to embodiments of the present invention.

FIG. 10 is a simplified diagram illustrating a digital high-pass filteraccording to embodiments of the present invention.

FIG. 11 provides plots showing simulated CDR error transfer functionpeaking (top) and output jitter (bottom) as function of Frac-N PLLbandwidth with digital high-pass filter.

FIG. 12 is a simplified diagram illustrating a small signal model for aFrac-N PLL with charge pump according to embodiments of the presentinvention.

FIG. 13 is a simplified diagram illustrating a Frac-N PLL implementationwith a charge pump according to embodiments of the present invention.

FIG. 14 shows the simulated CDR error transfer function peaking (top)and output jitter (bottom) as function of Frac-N PLL bandwidth withcharge pump in the feedforward path.

FIG. 15 is a simplified small signal model for a Frac-N PLL withfeed-forward VCO path according to embodiments of the present invention.

FIG. 16 is a simplified diagram illustrating a Frac-N PLL implementedwith feed-forward VCO path according to embodiments of the presentinvention.

FIG. 17 shows the simulated CDR error transfer function peaking (top)and output jitter (bottom) as function of Frac-N PLL bandwidth with afeed-forward VCO path.

FIG. 18 shows the effect of gain mismatch on CDR error transfer functionpeaking.

FIG. 19 is a simplified block diagram illustrating feedforward gaincalibration for Frac-N PLL implementation of CDR according toembodiments of the present invention.

FIG. 20 shows transfer functions for each of the two paths. It is to benoted that signal injected in Frac-N PLL path at frequency F₂ has thesame gain compared to the signal injected at frequency F₁ in thefeedforward path.

FIG. 21 is a simplified diagram illustrating a feedforward configurationwith injected signals according to embodiments of the present invention.

FIG. 22 provides simulation results of a feedforward implementationaccording to embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to data communication and electricalcircuits. More specifically, embodiments of the present inventionprovide a clock and data recovery (CDR) architecture implementation forhigh data rate wireline communication links. In an embodiment, a CDRdevice includes a phase detector, a loop filter, and a fractional-N PLL.The fractional-N PLL generates output clock signal based on output ofthe loop filter. There are other embodiments as well.

Low-jitter CDR architectures are often an essential aspect for high datarate wireline receivers. While some of the early CDRs utilized analogvoltage-controlled oscillator (VCO) based architectures, phaseinterpolator (PI)-based clock data recovery (CDR) modules have come todominate CDR loop implementations due to their relative small-area (ascompared to other designs and architectures) and digital controlfunctionality. A shift towards analog-to-digital converter (ADC) basedreceivers (thus moving from analog to digital) has made digital controlnecessary for CDR loop implementations. Phase interpolators provide thisfunctionality by converting digital phase control input signal to analogclock phase shift signal at the output. Performance of a PI in a CDRimplementation requires high linearity, high output phase resolution,and high-clock-frequency operation. Unfortunately, designing highlylinear PIs with high output phase resolution at high clock frequency isdifficult.

As a result, CDR architectures utilizing PIs struggle to achieve thelow-jitter performance criteria needed for high data rate operation. Analternative to PI-based CDR is a digitally controlled oscillator (DCO)based CDR architecture. The low-jitter requirement mentioned aboveprecludes the use of ring oscillator based DCOs applications thatrequire high data rates. For example, LC-based DCO (LC DCO) canpotentially provide low jitter, but they are susceptible toelectromagnetic coupling due to low CDR bandwidth achieved by typicalhigh data rate links.

It is thus to be appreciated that embodiments of the present inventionprovide high-performance CDRs implemented with fractional-N (Frac-N)phase-lock loops (PLL). More specifically, embodiments of the presentinvention provide CDRs with wide bandwidth Frac-N PLLs to provide thefunctionalities of digitally controlled oscillators and reducesusceptibility of LC-VCOs to electromagnetic coupling, while providinglow jitter digital phase shift capability to CDR loops. In an exemplaryembodiment, a CDR architecture is designed to eliminate the need forphase interpolator (PI) by employing fractional-N phase-locked loop(PLL), and it is capable of achieving low-jitter performance criticalfor high-data rate applications. The present invention also providesmethods to ensure CDR loop stability. The present invention additionallyprovides calibration technique to ensure robust operation. As anexample, the following techniques are provided:

-   -   Use of fractional-N (analog or digital) PLLs in CDR loops for        phase and frequency tracking;    -   Digital high-pass filter based technique for compensating        adverse effects (such as stability and error transfer function        peaking) caused due to introduction of Frac-N PLL in CDR loop;    -   Charge pump feedforward techniques for compensating adverse        effects (such as stability and error transfer function peaking)        caused due to introduction of Frac-N PLL in CDR loop;        -   A variation of this technique can be used for digital            fractional-N PLLs;    -   VCO feedforward techniques for compensating adverse effects        (such as stability and error transfer function peaking) caused        due to introduction of an analog or digital Frac-N PLL in CDR        loop;    -   VCO feedforward gain calibration techniques for in-situ        calibration of parallel path gain mismatch in VCO feedforward        scheme.

The following description is presented to enable one of ordinary skillin the art to make and use the invention and to incorporate it in thecontext of particular applications. Various modifications, as well as avariety of uses in different applications will be readily apparent tothose skilled in the art, and the general principles defined herein maybe applied to a wide range of embodiments. Thus, the present inventionis not intended to be limited to the embodiments presented, but is to beaccorded the widest scope consistent with the principles and novelfeatures disclosed herein.

In the following detailed description, numerous specific details are setforth in order to provide a more thorough understanding of the presentinvention. However, it will be apparent to one skilled in the art thatthe present invention may be practiced without necessarily being limitedto these specific details. In other instances, well-known structures anddevices are shown in block diagram form, rather than in detail, in orderto avoid obscuring the present invention.

The reader's attention is directed to all papers and documents which arefiled concurrently with this specification and which are open to publicinspection with this specification, and the contents of all such papersand documents are incorporated herein by reference. All the featuresdisclosed in this specification, (including any accompanying claims,abstract, and drawings) may be replaced by alternative features servingthe same, equivalent or similar purpose, unless expressly statedotherwise. Thus, unless expressly stated otherwise, each featuredisclosed is one example only of a generic series of equivalent orsimilar features.

Furthermore, any element in a claim that does not explicitly state“means for” performing a specified function, or “step for” performing aspecific function, is not to be interpreted as a “means” or “step”clause as specified in 35 U.S.C. Section 112, Paragraph 6. Inparticular, the use of “step of” or “act of” in the Claims herein is notintended to invoke the provisions of 35 U.S.C. 112, Paragraph 6.

Please note, if used, the labels left, right, front, back, top, bottom,forward, reverse, clockwise and counter clockwise have been used forconvenience purposes only and are not intended to imply any particularfixed direction. Instead, they are used to reflect relative locationsand/or directions between various portions of an object.

FIG. 1 is a simplified diagram illustrating a fractional-N PLL accordingto an embodiment of the present invention. This diagram is merely anexample, which should not unduly limit the scope of the claims. One ofordinary skill in the art would recognize many variations, alternatives,and modifications. The PLL includes a phase detector (PD) or phase andfrequency detector (PFD), a charge pump (CP), an analog loop filter(ALF), a voltage-controlled oscillator (VCO), multi-modulus divider(MMD), and a digital ΔΣ modulator (ΔΣ). The input reference clock isdenoted as CLK_(REF), and the output clock is denoted as CLK_(OUT). Ahigh resolution digital frequency control signal, D_(CTRL), is convertedto an integer division ratio, N_(DIV), by a digital ΔΣ modulator. Theoutput of the multi-modulus divider (MMD) is divided clock signaldenoted as CLK_(DIV). The output frequency, F_(OUT), of such afractional-N PLL depends on the input reference frequency F_(REF) andD_(CTRL), which is described in Equation 1 below:F _(OUT) =D _(CTRL) F _(REF)  Equation 1:

It is to be noted that D_(CTRL) can be used to control not only theoutput frequency, but also the output phase of the Frac-N PLL. FIG. 2provides a small signal model of a multi-modulus divider according toembodiments of the present invention. This diagram is merely an example,which should not unduly limit the scope of the claims. One of ordinaryskill in the art would recognize many variations, alternatives, andmodifications. It can be shown that the overall output phase of the MMDis given by Equation 2 below:

$\begin{matrix}{{\Phi_{DIV}(z)} = {{N_{nom}{\Phi_{OUT}(z)}} + {2{\pi\left( {{N_{DIV}(z)} - N_{nom}} \right)}\left( \frac{z^{- 1}}{1 - z^{- 1}} \right)}}} & {{Equation}\mspace{14mu} 2}\end{matrix}$

where Φ_(DIV) is the phase of the divider output, Φ_(OUT) is the phaseof the fractional-N PLL output that is input to the MMD, N_(nom) denotesthe nominal division ratio of the fractional-N PLL, and N_(DIV) denotesthe instantaneous integer division ratio of MMD.

Equation 2 can be expressed as Equation 3:

$\begin{matrix}{{\Phi_{DIV}(z)} = {{N_{nom}{\Phi_{OUT}(z)}} + {2{\pi\left( {{{D_{CTRL}(z)}{{STF}(z)}} - N_{nom}} \right)}\left( \frac{z^{- 1}}{1 - z^{- 1}} \right)}}} & {{Equation}\mspace{14mu} 3}\end{matrix}$

where STF(z) is the signal transfer function of the digital ΔΣ modulatorand D_(CTRL) denotes the digital frequency control input. If we assumean ideal reference clock for the Frac-N PLL (i.e., Φ_(DIV)=0), theoutput phase is given by Equation 4 below:

$\begin{matrix}{{\Phi_{OUT}(z)} = {{- \frac{2\pi}{N_{nom}}}\left( {{{D_{CTRL}(z)}{{STF}(z)}} - N_{nom}} \right)\left( \frac{z^{- 1}}{1 - z^{- 1}} \right)}} & {{Equation}\mspace{14mu} 4}\end{matrix}$

Equation 4 shows that the output phase of the Frac-N PLL can becontrolled using digital frequency control signal, D_(CTRL).

FIG. 3 is a simplified diagram illustrating a DCO-based CDR loop. Thephase difference between incoming data, DIN, and sampling clockCLK_(OUT) is detected by a digital phase detector (Digital PD). As anexample, a proportional-integral path based digital loop filter (DigitalLF) is used to generate a digital frequency control word D_(CTRL) forthe DCO. The output frequency F_(OUT) of the DCO depends on D_(CTRL),and the output frequency (F_(OUT)) of the DCO (characterized by a DCOgain, K_(DCO)) is described in Equation 5 below:F _(OUT) =D _(CTRL) K _(DCO)  Equation 5:

It is to be appreciated that there are similarities between DCO andFrac-N PLL. In particular, the functionality of Frac-N PLL in CDRimplementations according to embodiments of the present invention isequivalent to a digitally controlled oscillator (DCO), with thefunctional characteristics K_(DCO)=F_(REF). In various embodiments, aFrac-N PLL is used as a functional equivalent of a DCO in a CDR loop.Compared to a stand-alone LC DCO implementation, a wide bandwidth Frac-NPLL provides better immunity to VCO coupling noise. Due to its closedloop operation, it also provides a DCO implementation with awell-defined process independent DCO gain, K_(DCO).

FIG. 4 is a simplified diagram illustrating a Frac-N PLL incorporatedinside a CDR loop according to embodiments of the present invention.This diagram is merely an example, which should not unduly limit thescope of the claims. One of ordinary skill in the art would recognizemany variations, alternatives, and modifications. The digital frequencycontrol word D_(CTRL) (generated for CDR loop) is used as a frequencycontrol input for a Frac-N PLL. The output clock generated by Frac-NPLL, CLK_(OUT), is used as a sampling clock for the CDR loop.

As explained above, Frac-N PLL in FIG. 4 provides functionalities andadvantages of an LC DCO without its penalties as used in a CDR. As anexample, Frac-N PLL includes a phase detector (PD) or a phase-frequencydetector (PFD) for phase detection, a charge pump for compensation, ananalog loop filter (ALF) for filtering. The Frac-N PLL additionallyincludes an oscillator, an MMD, and a digital ΔΣ modulator. It is to beappreciated that Frac-N PLL can be implemented in other ways as well. Itis to be understood CDRs according to the present invention can beimplemented using analog Frac-N PLLs or digital Frac-N PLLs.

The incorporation of a Frac-N PLL in a CDR also contributes to certainfunctional difference from an LC DCO implementation. After all, a Frac-NPLL is not the same as an LC DCO. More specifically, while a Frac-N PLLhas well-defined gain at low frequencies, its gain rolls off at highfrequencies due to low pass nature of the PLL. FIG. 5 is a simplifieddiagram illustrating small signal phase domain model of a CDR loop witha DCO.

In case of an ideal DCO, the gain is independent of frequency, (i.e.,K_(DCO)(s)=K_(DCO), where s is the reference modulation frequency). Thedigital loop filter is chosen to achieve appropriate CDR closed loopbandwidth and jitter tolerance. On the other hand, when Frac-N PLL isused (instead of DCO), the gain is given by K_(DCO)(s)=F_(REF)G(s),where G(s) is effective low-pass transfer function of the Frac-N PLL.Due to its low-pass nature, G(s) introduces additional poles in the CDRloop transfer function, which adversely affects the CDR loop stabilityand creates peaking in the CDR error transfer function E(s), where E(s)is defined by E(s)=Φ_(E)(s)/Φ_(IN)(s), subsequently degrading the jittertolerance of the CDR loop. Note that jitter tolerance and error transferfunction are related as JTOL(s)=1/E(s).

FIG. 6 is a simplified diagram illustrating a small signal model ofFrac-N PLL functioning as a DCO according to embodiments of the presentinvention. This diagram is merely an example, which should not undulylimit the scope of the claims. One of ordinary skill in the art wouldrecognize many variations, alternatives, and modifications. The functionF_(OUT)(s) represents the output frequency of the Frac-N PLL, whileΦ_(OUT)(s) represents its phase. The high-pass shaped quantization noiseof the digital ΔΣ modulator is denoted as E_(Q,NTF)(s). The behavior ofthe Frac-N PLL is described in Equation 6 below:

$\begin{matrix}{{\frac{F_{OUT}(s)}{D_{CTRL}(s)} = {\frac{F_{OUT}(s)}{E_{Q,{NTF}}(s)} = {F_{REF}{G(s)}}}}{{Where},{{G(s)} = \frac{{LG}(s)}{1 + {{LG}(s)}}}}} & {{Equation}\mspace{14mu} 6}\end{matrix}$

In Equation 6, LG(s) denotes the open loop gain of the Frac-N PLL. Toreduce CDR error transfer function E(s) peaking, the implementationneeds to increase the bandwidth of Frac-N PLL and by extending thebandwidth of G(s). This increased bandwidth, however, allows more noisefrom digital ΔΣ pass through. As a result, there is a trade-off betweenpeaking of E(s) and the output jitter of the Frac-N PLL. FIG. 7 is aplot illustrating CDR error transfer functions comparing ideal DCO andactual DCO implementation (e.g., with Frac-N PLL) with a pole thatcontributes to undesired error transfer function peaking.

FIG. 8 provides plots illustrating CDR error transfer function peaking(top) and Frac-N PLL jitter (bottom) as function of Frac-N PLLbandwidth. As can be seen in FIG. 8, the peaking is reduced at higherPLL bandwidth at the cost of worse jitter performance. For optimalsystem performance, the implementation needs to reduce the bandwidth forF_(OUT)(S)/E_(Q,NTF) (s) while maximizing the bandwidth forF_(OUT)(s)/D_(CTRL)(s).

In various embodiments, the present invention provides feedforwardtechniques to compensate the bandwidth limitations of Frac-N PLL. Theproblem discussed in the previous section can be solved by introducing afeedforward path from D_(CTRL)(s) to F_(OUT)(s). Such a feedforward pathcan decouple the transfer function seen by D_(CTRL)(s) from the transferfunction seen by E_(Q,NTF)(s). We propose the following methods forimplementing the feedforward path.

According to a specific embodiment, a Frac-N PLL is implemented in a CDRwith a digital high-pass filter. FIG. 9 is a simplified diagramillustrating a small signal model for a Frac-N PLL according toembodiments of the present invention. This diagram is merely an example,which should not unduly limit the scope of the claims. One of ordinaryskill in the art would recognize many variations, alternatives, andmodifications. It is to be appreciated that the addition of a digitalhigh-pass filter in the D_(CTRL) path can effectively counter thelow-pass nature of G(s). In this case, the DCO (i.e., DCO equivalentimplemented with Frac-N PLL as used in a CDR) transfer function is givenby Equation 7 below:

$\begin{matrix}{\frac{F_{OUT}(s)}{D_{CTRL}(s)} = {F_{REF}{H_{1}(s)}{G(s)}}} & {{Equation}\mspace{14mu} 7}\end{matrix}$

It is to be noted that the transfer function from E_(Q,NTF) to F_(OUT)remains unchanged. For example, for H₁(s)=G⁻¹(s), Equation 8 below isobtained:

$\begin{matrix}{\frac{F_{OUT}(s)}{D_{CTRL}(s)} = {{F_{REF}{G^{- 1}(s)}{G(s)}} = F_{REF}}} & {{Equation}\mspace{14mu} 8}\end{matrix}$

In practical implementations, a digital finite impulse response (FIR)filter can be used to approximately match the inverse of G(s).Furthermore, there is a possibility of noise in D_(CTRL) signal foldingback in Frac-N PLL in-band frequency region due to up-sampling in theFrac-N PLL. To alleviate this undesirable effect of out of band noise,an anti-aliasing filter is also provided in the D_(CTRL) path. Thisanti-aliasing filter can also be implemented as a digital FIR filter.FIG. 10 is a simplified diagram illustrating a digital high-pass filteraccording to embodiments of the present invention. This diagram ismerely an example, which should not unduly limit the scope of theclaims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. For example, a digital highpass filter H₁(s) includes an inverse filter H₁(z) and an anti-aliasingfilter AA(z).

FIG. 11 provides plots showing simulated CDR error transfer functionpeaking (top) and output jitter (bottom) as function of Frac-N PLLbandwidth with digital high-pass filter. It can be seen that the CDRerror transfer function peaking becomes almost independent of Frac-N PLLbandwidth. This allows for a Frac-N PLL bandwidth that optimizes thejitter performance.

In certain embodiments, a CDR is implemented with Frac-N PLL and acharge pump, where the charge part is configured on the feedforwardpath. FIG. 12 is a simplified diagram illustrating a small signal modelfor a Frac-N PLL with charge pump according to embodiments of thepresent invention. This diagram is merely an example, which should notunduly limit the scope of the claims. One of ordinary skill in the artwould recognize many variations, alternatives, and modifications. TheDCO (i.e., DCO equivalent implemented with Frac-N PLL as used in a CDR)transfer function is provided in Equation 9 below:

$\begin{matrix}{\frac{F_{OUT}(s)}{D_{CTRL}(s)} = {{F_{REF}{G(s)}} + {\frac{{sN}_{nom}}{\alpha\; I_{CP}}{H_{2}(s)}{G(s)}}}} & {{Equation}\mspace{14mu} 9}\end{matrix}$

where α and I_(CP) denote phase detector and charge pump gain,respectively. It is to be noted that the transfer function fromE_(Q,NTF) to F_(OUT) remains unchanged. If we choose

${{H_{2}(s)} = {\frac{\alpha\; I_{CP}F_{REF}}{{sN}_{nom}}\left( {{G^{- 1}(s)} - 1} \right)}},$

Equation 10 below is obtained:

$\begin{matrix}{\frac{F_{OUT}(s)}{D_{CTRL}(s)} = F_{REF}} & {{Equation}\mspace{14mu} 10}\end{matrix}$

This feedforward path implementation requires digital filter as well asa current mode ΔΣ digital-to-analog converter (IDAC). FIG. 13 is asimplified diagram illustrating a Frac-N PLL implementation with acharge pump according to embodiments of the present invention. Thisdiagram is merely an example, which should not unduly limit the scope ofthe claims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. The IDAC is configured withΔΣ modulator in the signal path as shown. It is to be understood whilePD and CP are shown in the same block in FIG. 13, they are implementedseparately.

FIG. 14 shows the simulated CDR error transfer function peaking (top)and output jitter (bottom) as function of Frac-N PLL bandwidth withcharge pump in the feedforward path. It can be seen that the CDR errortransfer function peaking becomes almost independent of Frac-N PLLbandwidth. This allows for choosing Frac-N PLL bandwidth that optimizesthe jitter performance.

In various embodiments, a Frac-N PLL is implemented with a feed-forwardVCO path as a part of a CDR device. FIG. 15 is a simplified small signalmodel for a Frac-N PLL with a feed-forward VCO path according toembodiments of the present invention. This diagram is merely an example,which should not unduly limit the scope of the claims. One of ordinaryskill in the art would recognize many variations, alternatives, andmodifications. As shown in FIG. 15, the VCO (with gain K_(VCO)) isconfigured on the feedforward path. The DCO (i.e., DCO equivalentimplemented with Frac-N PLL as used in a CDR) transfer function isdescribed in Equation 11 below:

$\begin{matrix}{\frac{F_{OUT}(s)}{D_{CTRL}(s)} = {{F_{REF}{G(s)}} + {\frac{{sN}_{nom}}{\alpha\; I_{CP}{H_{LPF}(s)}}{H_{3}(s)}{G(s)}}}} & {{Equation}\mspace{14mu} 11}\end{matrix}$

where H_(LPF)(s) denotes the equivalent low pass transfer function ofthe analog loop filter connected to charge pump output. It is to benoted that the transfer function from E_(Q,NTF) to F_(OUT) remainsunchanged. If we choose

${{H_{3}(s)} = \frac{F_{REF}}{K_{VCO}}},$Equation 12 below is obtained:

$\begin{matrix}{\frac{F_{OUT}(s)}{D_{CTRL}(s)} = F_{REF}} & {{Equation}\mspace{14mu} 12}\end{matrix}$

Since H₃(s) is a constant, this feedforward path implementation requiresonly a ΔΣ digital-to-analog converter. FIG. 16 is a simplified diagramillustrating a Frac-N PLL implemented with a feed-forward VCO pathaccording to embodiments of the present invention. This diagram ismerely an example, which should not unduly limit the scope of theclaims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. For example, the ΔΣdigital-to-analog converter can be implemented as a switching capacitorin the VCO as shown in FIG. 16. For example, a digital gain scalingfactor K_(VFF) is utilized to implement H₃(s) function.

FIG. 17 shows the simulated CDR error transfer function peaking (top)and output jitter (bottom) as function of Frac-N PLL bandwidth with aVCO on the feedforward path. It can be seen that the CDR error transferfunction peaking becomes almost independent of Frac-N PLL bandwidth.This allows for choosing a Frac-N PLL bandwidth that optimizes thejitter performance.

It is to be noted that a VCO contributes to Frac-N PLL feedforward gainvariation. As discussed before, the feedforward gain must match withFrac-N PLL K_(VCO) to achieve an all-pass transfer function fromD_(CTRL) to F_(OUT). This gain scaling is implemented in digital domain,whereas the K_(VCO) of the analog VCO varies with process, temperature,and supply voltage. As a result, there is a mismatch between the digitalgain scaling factor (K_(VFF)) and the Frac-N PLL gain. FIG. 18 shows theeffect of gain mismatch on CDR error transfer function peaking. Itindicates that for optimum performance, the digital path gain K_(VFF)needs to be calibrated to match the analog gain inside Frac-N PLL.

FIG. 19 is a simplified block diagram illustrating feedforward gaincalibration for Frac-N PLL implementation of CDR according toembodiments of the present invention. This diagram is merely an example,which should not unduly limit the scope of the claims. One of ordinaryskill in the art would recognize many variations, alternatives, andmodifications. More specifically, the foreground calibration techniqueillustrated in FIG. 9 involves matching digital feedforward path gainwith that of analog path. As discussed above, the gain in thefeedforward path (e.g., the H_(VFF)(s) function) is to be matched withthe gain Frac-N PLL path (e.g., the H_(FRAC)(S) function).

FIG. 20 shows transfer functions for each of the two paths. It is to benoted that signal injected in Frac-N PLL path at frequency F₂ has thesame gain compared to the signal injected at frequency F₁ in thefeedforward path. Variables F_(CDR) and F_(PLL) denote the bandwidthsfor CDR and Frac-N PLL respectively. To measure the output because ofthe injected signal, we utilize the CDR phase detector. Since the CDRphase detector provides digital output, it can be measured in-situ.

FIG. 21 is a simplified diagram illustrating a feedforward configurationwith injected signals according to embodiments of the present invention.This diagram is merely an example, which should not unduly limit thescope of the claims. One of ordinary skill in the art would recognizemany variations, alternatives, and modifications. Digital square wavesignals are injected through each path, and they create triangularsignals at the CDR phase detector output. By detecting the peak-to-peakvalue of the triangular waveforms digitally, we can find the gainmismatch and correct for it by digitally adjusting K_(VFF). FIG. 22provides simulation results of a feedforward implementation according toembodiments of the present invention. As an example, it shows that foran expected ratio 10 for peak to peak values, K_(VFF) path gain needs tomatch with Frac-N PLL path gain. For other scaling factors the ratio ofpeak-to-peak values deviates from 10.

It is to be appreciated that Frac-N PLLs can be implemented into CDRdevices in various ways. For example, the combination and configurationof charge pump, VCO, and/or other components of a Frac-N PLL can be usedto allow the Frac-N PLL to satisfy the requirements of CDR devices.

While the above is a full description of the specific embodiments,various modifications, alternative constructions and equivalents may beused. Therefore, the above description and illustrations should not betaken as limiting the scope of the present invention which is defined bythe appended claims.

What is claimed is:
 1. A clock data recovery (CDR) device comprising: afirst phase detection module configured to receive digital input signaland determine a difference between the digital input signal and anoutput clock signal; a loop filter module coupled to the phase detectormodule and configured to generate a frequency control word; and afractional-N phase lock loop (Frac-N PLL) configured to generate theoutput clock signal based on the frequency control word, the Frac-N PLLcomprising a sigma delta module, the Frac-N PLL comprising a voltagecontrolled oscillator configured on a feedforward signal path and acurrent mode digital-to-analog converter, the current modedigital-analog converter being directly coupled to output of the sigmadelta modules, wherein the CDR is characterized by an error transferfunction and Frac-N PLL is characterized by a bandwidth, the errortransfer function being substantially independent from the bandwidth,and wherein the first phase detection module is configured to calibratea gain parameter of the Frac-N PLL based at least on the output clocksignal by, injecting a digital square wave signal along the feedforwardsignal path to create a triangular signal at a phase detector output,detecting peak-to-peak value of a triangular waveform digitally to findgain mismatch, and correcting for the gain mismatch by adjusting adigital gain scaling factor (K_(VFF)) in situ.
 2. The CDR device ofclaim 1 further comprising a charge pump configured on the feedforwardsignal path.
 3. The CDR device of claim 1 wherein the first phasedetection module is coupled to a reference clock signal.
 4. The CDRdevice of claim 1 wherein the Frac-N PLL further comprises amulti-modulus divider.